(CPSR). The CPSR contains a number of flags which report and control the operation of the ARM7
CPU.
The top four bits of the CPSR contain the condition codes which are set by the CPU. The condition codes report
the result status of a data processing operation. From the condition codes you can tell if a data processing
instruction generated a negative, zero, carry or overflow result. The lowest eight bits in the CPSR contain flags
which may be set or cleared by the application code. Bits 7 and 8 are the I and F bits. These bits are used to
enable and disable the two interrupt sources which are external to the ARM7 CPU. All of the LPC2000
peripherals are connected to these two interrupt lines as we shall see later. You should be careful when
programming these two bits because in order to disable either interrupt source the bit must be set to ‘1’ not ‘0’
as you might expect. Bit 5 is the THUMB bit.

The ARM7 CPU is capable of executing two instruction sets; the ARM instruction set which is 32 bits wide and
the THUMB instruction set which is 16 bits wide. Consequently the T bit reports which instruction set is being
executed. Your code should not try to set or clear this bit to switch between instruction sets. We will see the
correct entry mechanism a bit later. The last five bits are the mode bits. The ARM7 has seven different
operating modes. Your application code will normally run in the user mode with access to the register bank R0 –
R15 and the CPSR as already discussed. However in response to an exception such as an interrupt, memory
error or software interrupt instruction the processor will change modes. When this happens the registers R0 –
R12 and R15 remain the same but R13 (LR ) and R14 (SP) are replaced by a new pair of registers unique to
that mode. This means that each mode has its own stack and link register. In addition the fast interrupt mode
(FIQ) has duplicate registers for R7 – R12. This means that you can make a fast entry into an FIQ interrupt
without the need to preserve registers onto the stack.