chapter 1 ARM Architecture
This chapter outlines the ARM processor's architecture and describes the syntax rules of the ARM
assembler. Later chapters describe the ARM's stack and exception processing system
in more detail.
Figure 1.1 on the following page shows the internal structure of the ARM processor. The ARM
is a Reduced Instruction Set Computer (RISC) system and includes the attributes typical to that
type of system:
• A large array of uniform registers.
• A load/store model of data-processing where operations can only operate on registers and not
directly on memory. This requires that all data be loaded into registers before an operation
can be preformed, the result can then be used for further processing or stored back into
memory.
• A small number of addressing modes with all load/store addresses begin determined from
registers and instruction elds only.
• A uniform xed length instruction (32-bit).
In addition to these traditional features of a RISC system the ARM provides a number of additional
features:
• Separate Arithmetic Logic Unit (ALU) and shifter giving additional control over data processing
to maximize execution speed.
• Auto-increment and Auto-decrement addressing modes to improve the operation of program
loops.
• Conditional execution of instructions to reduce pipeline ushing and thus increase execution
speed.