http://www.8051projects.net/ Learn to make simple microcontroller projects, pic, 8051, avr and arm projects. download 8051 projects, tutorials, libraries, sample codes. join the microcontroller discussion forum and ask doubts regarding electronics. the best source for 8051 over internet. en-gb 2008-12-01T23:04:55-08:00 contact@nospam.com hourly 1 2000-01-01T12:00+00:00 http://www.8051projects.net/forum-t5633.html 2008-12-01T23:04:55-08:00 please do not post on this thread for doubts post on http://www.8051projects.net/forum-t5636-last.html chapter 1 ARM ArchitectureThis chapter outlines the ARM processor's architecture and describes the syntax rules of the ARMassembler. Later chapters describe the ARM's stack and exception processing systemin more detail.Figure 1.1 on the following page shows the internal structure of the ARM processor. The ARMis a Reduced Instruction Set Computer (RISC) system and includes the attributes typical to thattype of system:• A large array of uniform registers.• A load/store model of data-processing where operations can only operate on registers and notdirectly on memory. This requires that all data be loaded into registers before an operationcan be preformed, the result can then be used for further processing or stored back intomemory.• A small number of addressing modes with all load/store addresses begin determined fromregisters and instruction elds only.• A uniform xed length instruction (32-bit).In addition to these traditional features of a RISC system the ARM provides a number of additionalfeatures:• Separate Arithmetic Logic Unit (ALU) and shifter giving additional control over data processingto maximize execution speed.• Auto-increment and Auto-decrement addressing modes to improve the operation of programloops.• Conditional execution of instructions to reduce pipeline ushing and thus increase executionspeed. http://www.8051projects.net/forum-t5633.html 2008-12-01T23:04:55-08:00 shyam 1.1 Processor modesThe ARM supports the seven processor modes shown in table1.1.Mode changes can be made under software control, or can be caused by external interrupts orexception processing.Most application programs execute in User mode. While the processor is in User mode, theprogram being executed is unable to access some protected system resources or to change mode,other than by causing an exception to occur (see 1.4 ). This allows a suitably writtenoperating system to control the use of system resources. http://www.8051projects.net/forum-t5633.html 2008-12-01T23:04:55-08:00 shyam table1.1 http://www.8051projects.net/forum-t5633.html 2008-12-01T23:04:55-08:00 shyam The modes other than User mode are known as privileged modes. They have full access to systemresources and can change mode freely. Five of them are known as exception modes: FIQ (FastInterrupt), IRQ (Interrupt), Supervisor, Abort, and Undened. These are entered when specicexceptions occur. Each of them has some additional registers to avoid corrupting User mode statewhen the exception occurs (see 1.2 for details).The remaining mode is System mode, it is not entered by any exception and has exactly the sameregisters available as User mode. However, it is a privileged mode and is therefore not subject tothe User mode restrictions. It is intended for use by operating system tasks which need access tosystem resources, but wish to avoid using the additional registers associated with the exceptionmodes. Avoiding such use ensures that the task state is not corrupted by the occurrence of anyexception. http://www.8051projects.net/forum-t5633.html 2008-12-01T23:04:55-08:00 shyam 1.2 RegistersThe ARM has a total of 37 registers. These comprise 30 general purpose registers, 6 status registersand a program counter. Figure 1.2 illustrates the registers of the ARM. Only fteen of the generalpurpose registers are available at any one time depending on the processor mode.There are a standard set of eight general purpose registers that are always available (R0  R7) nomatter which mode the processor is in. These registers are truly general-purpose, with no specialuses being placed on them by the processors' architecture.A few registers (R8  R12) are common to all processor modes with the exception of the qmode. This means that to all intent and purpose these are general registers and have no specialuse. However, when the processor is in the fast interrupt mode these registers and replaced withdierent set of registers (R8_q - R12_q). Although the processor does not give any specialpurpose to these registers they can be used to hold information between fast interrupts. You canconsider they to be static registers. The idea is that you can make a fast interrupt even fasterby holding information in these registers.The general purpose registers can be used to handle 8-bit bytes, 16-bit half-words1, or 32-bitwords. When we use a 32-bit register in a byte instruction only the least signicant 8 bits areused. In a half-word instruction only the least signicant 16 bits are used. Figure 3.3 demonstratesthis.The remaining registers (R13  R15) are special purpose registers and have very specic roles:R13 is also known as the Stack Pointer, while R14 is known as the Link Register, and R15 isthe Program Counter. The user (usr) and System (sys) modes share the same registers. Theexception modes all have their own version of these registers. Making a reference to register R14will assume you are referring to the register for the current processor mode. If you wish to refer to the user mode version of this register you have refer to the R14_usr register. You may onlyrefer to register from other modes when the processor is in one of the privileged modes, i.e., anymode other than user mode.There are also one or two status registers depending on which mode the processor is in. The CurrentProcessor Status Register (CPSR) holds information about the current status of the processor(including its current mode). In the exception modes there is an additional Saved Processor StatusRegister (SPSR) which holds information on the processors state before the system changed intothis mode, i.e., the processor status just before an exception. http://www.8051projects.net/forum-t5633.html 2008-12-01T23:04:55-08:00 shyam fig1.2 http://www.8051projects.net/forum-t5633.html 2008-12-01T23:04:55-08:00 shyam 1.2.1 The stack pointer, SP or R13Register R13 is used as a stack pointer and is also known as the SP register. Each exception modehas its own version of R13, which points to a stack dedicated to that exception mode. 1 .2.2 The Link Register, LR or R14Register R14 is also known as the Link Register or LR.It is used to hold the return address for a subroutine. When a subroutine call is performed via aBL instruction, R14 is set to the address of the next instruction. To return from a subroutine youneed to copy the Link Register into the Program Counter. This is typically done in one of the twoways:• Execute either of these instructions:MOV PC, LR or BAL LR• On entry to the subroutine store R14 to the stack with an instruction of the form:STMFD SP!,{hregistersi, LR}and use a matching instruction to return from the subroutine:LDMFD SP!,{hregistersi, PC}This saves the Link Register on the stack at the start of the subroutine. On exit from thesubroutine it collects all the values it placed on the stack, including the return address thatwas in the Link Register, except it returns this address directly into the Program Counterinstead.