Discussion in "New Ideas regarding projects" started by    iec    Sep 9, 2014.
Tue Sep 09 2014, 05:17 AM
#1
HI ALL

I try to implement same code in master and slave for spi communication. Is it possible to do so? In detail, master will have code for both master_init and slave_init. The exact replica will be in slave controller. Which ever turns on first, it needs to configured as master and the other one as slave. This is my requirement. Innovative ideas, suggestions, h/w suggestions are requested on this concept
Thu Sep 11 2014, 04:44 AM
#2
master will always lower down the Chip select... so who so ever lowers the chip select pin of other controller will be the master. thats the simplest thing I can think of. You can put chip select as input in both controller from start and if possible keep it on interrupt pin so it becomes a highest priority. as soon as interrupt comes you set the mode as slave for the controller and controller who is putting CS low will be come master automatically.

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Fri Sep 29 2017, 02:45 AM
Maaz
i am doing the same project on verilog please contact me [email protected]
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Fri Aug 18 2017, 11:37 AM
hi @ angel patel i will attach a file i hope it will be helpfull for you
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Mon Aug 14 2017, 09:57 PM
@ angel patel... just log in and post your problem
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Thu Jul 27 2017, 12:05 PM
okay fine

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