Discussion in "Project Help" started by    scorcho    Oct 5, 2006.
Mon Oct 09 2006, 09:26 pm
#11
I wasn't talking about the parity bit but rather the stop bit. Anyway, I wasn't gonnna use an 8051. I'm actually using a Toshiba 16bit MCU that doesn't have a configurable stop bit, but I figure if I just delay sending the next byte for 1 etu in software with some kinda delay, it *should* work.
Mon Oct 09 2006, 10:47 pm
#12
thats what i was talkin about.. so this can help you in dealing with the error detection part maybe solved by this..
Thu Oct 12 2006, 11:10 am
#13
Well, I'm writing the UART code now with interrupts, but I'm having trouble coming up with a way of pulling the I/O line low when receiving a byte from the smart card. I'm putting my parity error detection logic in my receivebyte ISR, and checking the UART status bits for a parity error. If there no error I'll go ahead and copy the UART buffer to a variable, but if there is I'll have to pull the I/O line low.

The trouble comes because I'm not sure at which point in the UART transmission the ISR is called. According to UART standards and my MCU datasheet, the buffer is double buffered, and the interrupt is generated when 8 bits have been transferred from buffer1 to buffer2. Does this include the parity/stop bit? i.e. in my ISR, can I assume that the transmission is currently in the "stop bits" portion, so that I can pull the I/O line low? I don't want to be pulling the I/O line low when the sender is still sending the parity bit(too early), or when the stop bits have already passed(too late).

And regarding pulling the I/O line low for 1 etu, how do I even do that? If I enable my TX interrupt and set my UART buffer to 0 , wouldn't that send 8 bits of 0 complete with start/stop bits? How can I specifically pull it low for just 1 UART cycle?
Thu Oct 12 2006, 08:05 pm
#14
you will get the interrupt during reception when.. sender is about to send the stop bit. and yes.. parity bit has been recieved already at that moment. coz its a part of data now. so you can assume that parity with data has recieved.. but. now..the thing is.. you should be doing the checking of parity fast.. coz.. u cant waste time.. in checking the parity bit.. coz.. there is no point in making the TX line low after the sender has already sent the stop bit..

and.. regaring the duration of pulling the I/O line.. 1ETU is too much... and seems wastage of time.. so.. and.. ofcourse your sender understands the protocol.. and.. 1 UART cycle is sufficient.. you can define a global parity check bit.. which will be set when u recieve a parity error.. and.. in the parity check routine itself you can pull down the TX line(as its software implemented so everything is in our hand) and.. i think problem is solved... hope so..

Get Social

Information

Powered by e107 Forum System

Downloads

Comments

Bobbyerilar
Thu Mar 28 2024, 08:08 am
pb58
Thu Mar 28 2024, 05:54 am
Clarazkafup
Thu Mar 28 2024, 02:24 am
Walterkic
Thu Mar 28 2024, 01:19 am
Davidusawn
Wed Mar 27 2024, 08:30 pm
Richardsop
Tue Mar 26 2024, 10:33 pm
Stevencog
Tue Mar 26 2024, 04:26 pm
Bernardwarge
Tue Mar 26 2024, 11:15 am