Discussion in "ARM Development" started by    shyam    Dec 30, 2007.
Sun Dec 30 2007, 09:15 pm
here we will discuss the various sorces of interrupts and how to handle them....
Mon Dec 31 2007, 12:33 am
before starting lets have a litle discussion on the most important registers which u wud consider while programming for interrupt sources.... it is like the PSW for 51 family

lpcbooksrn from hitech

(CPSR). The CPSR contains a number of flags which report and control the operation of the ARM7
The top four bits of the CPSR contain the condition codes which are set by the CPU. The condition codes report
the result status of a data processing operation. From the condition codes you can tell if a data processing
instruction generated a negative, zero, carry or overflow result. The lowest eight bits in the CPSR contain flags
which may be set or cleared by the application code. Bits 7 and 8 are the I and F bits. These bits are used to
enable and disable the two interrupt sources which are external to the ARM7 CPU. All of the LPC2000
peripherals are connected to these two interrupt lines as we shall see later. You should be careful when
programming these two bits because in order to disable either interrupt source the bit must be set to ‘1’ not ‘0’
as you might expect. Bit 5 is the THUMB bit.

The ARM7 CPU is capable of executing two instruction sets; the ARM instruction set which is 32 bits wide and
the THUMB instruction set which is 16 bits wide. Consequently the T bit reports which instruction set is being
executed. Your code should not try to set or clear this bit to switch between instruction sets. We will see the
correct entry mechanism a bit later. The last five bits are the mode bits. The ARM7 has seven different
operating modes. Your application code will normally run in the user mode with access to the register bank R0 –
R15 and the CPSR as already discussed. However in response to an exception such as an interrupt, memory
error or software interrupt instruction the processor will change modes. When this happens the registers R0 –
R12 and R15 remain the same but R13 (LR ) and R14 (SP) are replaced by a new pair of registers unique to
that mode. This means that each mode has its own stack and link register. In addition the fast interrupt mode
(FIQ) has duplicate registers for R7 – R12. This means that you can make a fast entry into an FIQ interrupt
without the need to preserve registers onto the stack.

[ Edited Mon Jan 21 2008, 07:52 pm ]
 schu like this.
Mon Dec 31 2007, 01:00 am
Sat Feb 07 2009, 09:02 pm

I've been tinkering with the following interrupt code for a while but i'm getting a little stuck here.

My goal is to generate a pulstrain of 20ms with a high of 1,5ms.
I got the interrupt fire but it only does a IOSET and when the ISR is finished (depending on the T0MR0) it should do a IOCLR.

Does anyone have sugestions for this?

#include "LPC214x.h"
#include "VIClowlevel.h"
#define PLOCK 0x400
void init(void);
void IRQ_ON (void)   __attribute__ ((interrupt("IRQ")));
void FIQ_Routine (void)   __attribute__ ((interrupt("FIQ")));
void SWI_Routine (void)   __attribute__ ((interrupt("SWI")));
void UNDEF_Routine (void) __attribute__ ((interrupt("UNDEF")));

int main(void)
    int i;
    IODIR0 = 0x00200000;
    IOCLR0 = 0x00200000;                    //LEDs off
//    PINSEL1 = 0x00002003;                   //P0.16 as CAP0.2 P0.22 CAP0.0

//    init();
    T0TCR = 0x02;                           //reset counter
    T0IR = 0xff;
    T0MCR = 0x00000003;                     //interrupt and reset on MR0 + Interrupt MR1
    T0MR0 = 0x03938700;                     //cycletime 1sec
//    T0TCR = 0x00000002;                     //Reset counter
//    T0CCR = 0x00000005;                     //Capture on rising edge + interrupt
    T0TCR = 0x00000001;                     //enable timer
    VICVectCntl0 = 0x00000024;              //use it for Timer 0 Interrupt:
    VICVectAddr0 = (unsigned)IRQ_ON;        //set interrupt vector in 0
    VICIntEnable = 0x00000010;              //enable TIMER0 interrupt

void IRQ_ON(void)
    int i;
    IOSET0 = 0x30600000;        //4 LEDs blink
    IOCLR0 = 0x30600000;
    T0IR = 0x01;                //clear interrupt
    VICVectAddr = 0;            //end of interrupt - dummy write

void init(void)
    PLLCFG=0x24;                //set multiplier/divider values
    PLLCON=0x01;                //enable PLL
    while(!(PLLSTAT & PLOCK));  //wait for the PLL to lock to set frequency
    PLLCON=0x3;                 //connect the PLL as the clock source
    MAMCR=0x02;                 //enable MAM
    MAMTIM=0x04;                //set number of clocks for flash memory fetch
    VPBDIV=0x01;                //set peripheral clock(pclk) to system clock(cclk)

void FIQ_Routine(void){
    while (1) ; 
void SWI_Routine(void){
    while (1) ; 
void UNDEF_Routine(void) {
	while (1) ;	

Thank you.


Sun Feb 22 2009, 09:42 pm
how would u say that it doesnt do a IOclr ?

actually u can see the IOset cause there is a delay afterwards.. and soon after the isr finishes u get another timer interrupt!

do these..
1. stop the timer as soon as u get in the ISR (pause timer)
2.put a delay after the IOCLR command

now see if it works

Mon Feb 23 2009, 07:20 pm
this was suppose to be a tutorial thread
shyam i told you put everything in word document, its easy for u to make it in free time
rest leave on me
Tue Feb 24 2009, 12:37 pm

Sat Jun 12 2010, 04:35 pm
We can assign the addresses for 16 IRQ interrupts, what about FIQ interrupt?
And i also have doubt on VIC? What is necessity of VICSOFTINT? When we set UART0 interrupt in VICSOFTINT register, what we will be the status of U0LSR register?
Mon Jun 14 2010, 12:52 am
I have made reply to you in doubts thread, check it.
Wed Jun 29 2011, 06:13 pm
my name is Koteswara rao.iam working in ism ,hyderabad.
has a Embedded developer.present iam working module is lpc2129.
please guided them on interrrupts &timers on lpc2129
 manjunathsg85 like this.

Get Social


Powered by e107 Forum System



Tue May 21 2024, 02:06 am
Sun May 19 2024, 05:39 pm
Sun May 19 2024, 03:06 pm
Sun May 19 2024, 07:39 am
Sat May 18 2024, 07:28 am
Fri May 17 2024, 06:14 pm
Fri May 17 2024, 10:28 am
Fri May 17 2024, 10:19 am