What is I2C?

I2C Bus

In modern electronic systems there are a number of peripheral ICs that have to communicate with each other and the outside world. To maximize hardware efficiency and simplify circuit design, Philips developed a simple bi-directional 2-wire, serial data (SDA) and serial clock (SCL) bus for inter-IC control. This I2C-bus supports any IC fabrication process and, with the extremely broad range of I2C-compatible chips from Philips and other suppliers, it has become the worldwide industry standard proprietary control bus. Each device is recognized by a unique address and can operate as either a receiver-only device (e.g. an LCD Driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. I2C is a multi-master bus, i.e. it can be controlled by more than one IC connected to it.

The basic I2C-bus, with a data transfer rate up to 100 kbits/s and 7-bit addressing, was originally introduced nearly 20 years ago. But, as data transfer rates and application functionality rapidly increased, the I2C-bus specification was enhanced to include Fast-mode and 10-bit addressing, meeting the demand for higher speeds and more address space. Most recently, High-speed Mode has been added; with speeds of up to 3.4 Mbits/s it ensures the capacity of the I2C-bus to support existing and future high speed serial transfer rates for applications such as EEPROM and Flash memory.

I2C Bus Specification and Concept

The I2C-bus supports any IC fabrication process (NMOS, CMOS, bipolar). Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus. Each device is recognized by a unique address (whether it's a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. Obviously an LCD driver is only a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Table 1). A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.

Term Description
Transmitter The device which sends the data to the bus.
Receiver The device which receives the data from the bus.
Master The device which initiates a transfer, generates clock signals and terminates a transfer.
Slave The device addressed by a master.
Multi-Master More than one master can attempt to control the bus.
Arbitration Only one master can control the bus.
Synchronization Procedure to sync. the clock signal.

The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually micro-controllers, let's consider the case of a data transfer between two microcontrollers connected to the I2C-bus (see figure above).

1) Suppose microcontroller A wants to send information to microcontroller B: [list]*Microcontroller A (master), addresses microcontroller B (slave). *Microcontroller A (master-transmitter), sends data to microcontroller B (slave-receiver). *Microcontroller A terminates the transfer.[/list] 2) If microcontroller A wants to receive information from microcontroller B: [list]*Microcontroller A (master) addresses microcontroller B (slave). *Microcontroller A (master-receiver) receives data from microcontroller B (slave-transmitter). *Microcontroller A terminates the transfer.[/list] Generation of clock signals on the I2C-bus is always the responsibility of master devices; each master generates its own clock signals when transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow-slave device holding-down the clock line or by another master when arbitration occurs.

Data Validity Condition

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (see Fig.4).

I2C Data Validity condition

Start and Stop Condition

A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case. This situation indicates a START condition.

A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition.

The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical (see Fig.6). For the remainder of this document, therefore, the S symbol will be used as a generic term to represent both the START and repeated START conditions, unless Sr is particularly relevant.

Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. However, microcontrollers with no such interface have to sample the SDA line at least twice per clock period to sense the transition.

I2C Start and Stop condition

Data Transfer

Byte Format:

Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first (see Fig.6). If a slave can't receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL.

In some cases, it's permitted to use a different format from the I2C-bus format (for CBUS compatible devices for example). A message which starts with such an address can be terminated by generation of a STOP condition, even during the transmission of a byte. In this case, no acknowledge is generated.

I2C Data Transfer
Acknowledge:

Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse.

The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse (see Fig.7). Of course, set-up and hold times must also be taken into account.

Usually, a receiver which has been addressed is obliged to generate an acknowledgement after each byte has been received. The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer.

If a slave-receiver does acknowledge the slave address but, some time later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave generating the not-acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates a STOP or a repeated START condition.

If a master-receiver is involved in a transfer, it must signal the end of data to the slave- transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must release the data line to allow the master to generate a STOP or repeated START condition.

I2C Acknowledge

Conversation

Thu Jan 29 2015, 11:24 AM
durai
I found discussion relevant to my problem (link:http://www.8051projects.net/t59199/gsm-cdma-discussion/flashing-new-firmware-in-sim900-modem.htm) but i could not find the project mentioned in that discusion
Thu Jan 29 2015, 11:21 AM
durai
Hi i am using a SIM/900A GSM modem, I want to send email with an attachement using a microcontroller but when i try to use AT_Email commands it gives me error,I think modem doesnot support those commands,is there any other way to send mail using that modem??
ajay_bhargav
Thu Jan 29 2015, 06:54 AM
@gaurav, please mail me message you're trying to post.
ExperimenterUK
Thu Jan 29 2015, 01:17 AM
bhagyesh.bhavasar/gaurav.k I can post with Firefox. Can you try other browsers ?
naqirizvi
Wed Jan 28 2015, 08:08 AM
the web theme is too much buggy and heavy , admin please change it to simple theme, so that user can browse quickly
naqirizvi
Wed Jan 28 2015, 08:07 AM
some one please share software name or ebooks related to avr
bhagyesh.bhavasar
Tue Jan 27 2015, 11:06 AM
i want to share my project but there is problem occurred during postng
bhagyesh.bhavasar
Tue Jan 27 2015, 05:58 AM
@ExperimentalUK i have used that purple button but same as previous it takes me to blank page
ExperimenterUK
Sun Jan 25 2015, 08:10 PM
This box is for chat. Post problems in a suitable forum
ExperimenterUK
Sun Jan 25 2015, 08:04 PM
@gaurav.k Use the purple "Post reply" button. Green buttons often present a fresh edit box.

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